| Logical effort of CNFET-based circuits in the presence of metallic tubes M Ali, R Ashraf, M Chrzanowska-Jeske Nanotechnology (IEEE-NANO), 2012 12th IEEE Conference on, 1-6, 2012 | 12 | 2012 |
| Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization M Ali, MA Ahmed, M Chrzanowska-Jeske IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018 | 10 | 2018 |
| Logical Effort model for CNFET circuits with CNTs variations M Ali, M Ahmed, M Chrzanowska-Jeske, J Morris Nanotechnology (IEEE-NANO), 2015 IEEE 15th International Conference on, 1218 …, 2015 | 8 | 2015 |
| Stochastic analysis of CNFET circuits using enhanced logical effort model in the presence of metallic tubes M Ali, M Ahmed, M Chrzanowska-Jeske Electronics, Circuits and Systems (ICECS), 2014 21st IEEE International …, 2014 | 7 | 2014 |
| Fast and accurate evaluation of delay in CNFET circuits M Ali, M Ahmed, M Chrzanowska-Jeske Nanotechnology (IEEE-NANO), 2016 IEEE 16th International Conference on, 659-662, 2016 | 6 | 2016 |
| Logical Effort model for CNFET-based circuits M Ali, M Ahmed, M Chrzanowska-Jeske Nanotechnology (IEEE-NANO), 2014 IEEE 14th International Conference on, 460-465, 2014 | 4 | 2014 |
| Efficient Methods for Robust Circuit Design and Performance Optimization for Carbon Nanotube Field Effect Transistors M Ali Portland State University, 2019 | 1 | 2019 |
| TSV stress-aware performance and reliability analysis M Ali, MA Ahmed, M Chrzanowska-Jeske Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International …, 2012 | 1 | 2012 |
