| A general decomposition for reversible logic M Perkowski, L Jozwiak, P Kerntopf, A Mishchenko, A Al-Rabadi, ... | 245 | 2001 |
| Using simulation and satisfiability to compute flexibilities in Boolean networks A Mishchenko, JS Zhang, S Sinha, JR Burch, R Brayton, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006 | 79 | 2006 |
| Regularity and symmetry as a base for efficient realization of reversible logic circuits M Perkowski, P Kerntopf, A Buller, M Chrzanowska-Jeske, A Mishchenko, ... | 73 | 2001 |
| An exact algorithm to minimize mixed-radix exclusive sums of products for incompletely specified Boolean functions M Perkowski, M Chrzanowska-Jeske 1990 IEEE International Symposium on Circuits and Systems (ISCAS), 1652-1655, 1990 | 71 | 1990 |
| A comprehensive approach to logic synthesis and physical design for two-dimensional logic arrays A Sarabi, N Song, M Chrzanowska-Jeske, MA Perkowski Proceedings of the 31st annual Design Automation Conference, 321-326, 1994 | 68 | 1994 |
| Regular realization of symmetric functions using reversible logic M Perkowski, P Kerntopf, A Buller, M Chrzanowska-Jeske, A Mishchenko, ... Proceedings Euromicro Symposium on Digital Systems Design, 245-252, 2001 | 65 | 2001 |
| BILOW-simulation of low-temperature bipolar device behavior M Chrzanowska-Jeske, RC Jaeger IEEE transactions on electron devices 36 (8), 1475-1488, 1989 | 59 | 1989 |
| Using a distributed rectangle bin-packing approach for core-based SoC test scheduling with power constraints Y Xia, M Chrzanowska-Jeske, B Wang, M Jeske ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003 | 55 | 2003 |
| Lattice diagrams using Reed-Muller logic MA Perkowski, M Chrzanowska-Jeske, Y Xu IFIP WG 10.5 Workshop on Applications of the Reed-Muller Expansion in …, 1997 | 45 | 1997 |
| Fast placement-aware 3-D floorplanning using vertical constraints on sequence pairs RK Nain, M Chrzanowska-Jeske IEEE transactions on very large scale integration (VLSI) systems 19 (9 …, 2010 | 44 | 2010 |
| Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability JS Zhang, A Mishchenko, R Brayton, M Chrzanowska-Jeske Proceedings of the 43rd annual Design Automation Conference, 510-515, 2006 | 35 | 2006 |
| A regular representation for mapping to fine-grain, locally-connected fpgas M Chrzanowska-Jeske, Z Wang, Y Xu 1997 IEEE International Symposium on Circuits and Systems (ISCAS) 4, 2749-2752, 1997 | 34 | 1997 |
| Board-level multiterminal net assignment for the partial cross-bar architecture X Song, WNN Hung, A Mishchenko, M Chrzanowska-Jeske, A Kennings, ... IEEE transactions on very large scale integration (VLSI) systems 11 (3), 511-514, 2003 | 31 | 2003 |
| Multi-level logic synthesis based on Kronecker decision diagrams and Boolean ternary decision diagrams for incompletely specified functions MA Perkowski, M Chrzanowska-Jeske, A Sarabi, I Schäfer Vlsi Design 3 (3-4), 301-313, 1995 | 31 | 1995 |
| Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs F Rafiq, M Chrzanowska-Jeske, HH Yang, N Sherwani Proceedings of the 2002 international symposium on Physical design, 56-61, 2002 | 30 | 2002 |
| Logic synthesis for a regular layout M Chrzanowska-Jeske, Y Xu, M Perkowski VLSI Design 10 (1), 35-55, 1999 | 30 | 1999 |
| Simulation and satisfiability in logic synthesis JS Zhang, S Sinha, A Mishchenko, RK Brayton, M Chrzanowska-Jeske computing 7, 14, 2005 | 27 | 2005 |
| Functional yield estimation of carbon nanotube-based logic gates in the presence of defects R Ashraf, M Chrzanowska-Jeske, SG Narendra IEEE transactions on nanotechnology 9 (6), 687-700, 2010 | 26 | 2010 |
| Efficient algorithms for creation of linearly-independent decision diagrams and their mapping to regular layouts M Perkowski, B Falkowski, M Chrzanowska-Jeske, R Drechsler VLSI design 14, 35-52, 2002 | 22 | 2002 |
| Mapping of symmetric and partially-symmetric functions to the CA-type FPGAs M Chrzanowska-Jeske, Z Wang 38th Midwest Symposium on Circuits and Systems. Proceedings 1, 290-293, 1995 | 22 | 1995 |
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