| Analytical modeling and simulation of multigate FinFET devices and the impact of high-k dielectrics on short channel effects (SCEs) V Narendar, RA Mishra Superlattices and Microstructures 85, 357-369, 2015 | 125 | 2015 |
| Design insights of nanosheet FET and CMOS circuit applications at 5-nm technology node VB Sreenivasulu, V Narendar IEEE Transactions on Electron Devices 69 (8), 4115-4122, 2022 | 73 | 2022 |
| Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes VB Sreenivasulu, V Narendar Microelectronics Journal 116, 105214, 2021 | 60 | 2021 |
| A comprehensive analysis of junctionless tri-gate (TG) FinFET towards low-power and high-frequency applications at 5-nm gate length VB Sreenivasulu, V Narendar Silicon, 1-13, 2021 | 56 | 2021 |
| Design and temperature assessment of junctionless nanosheet fet for nanoscale applications VB Sreenivasulu, V Narendar Silicon 14 (8), 3823-3834, 2021 | 51 | 2021 |
| Surface potential modeling of graded-channel gate-stack (GCGS) high-K dielectric dual-material double-gate (DMDG) MOSFET and analog/RF performance study V Narendar, KA Girdhardas silicon 10, 2865-2875, 2018 | 46 | 2018 |
| Design and Deep Insights into Sub-10 nm Spacer Engineered Junctionless FinFET for Nanoscale Applications B Sreenivasulu V., V Narendar ECS Journal of Solid State Science and Technology 10 (1), 013008, 2021 | 41 | 2021 |
| Junctionless SOI FinFET with advanced spacer techniques for sub-3 nm technology nodes VB Sreenivasulu, V Narendar AEU-International Journal of Electronics and Communications 145, 154069, 2022 | 40 | 2022 |
| Performance improvement of spacer engineered n-type SOI FinFET at 3-nm gate length VB Sreenivasulu, V Narendar AEU-International Journal of Electronics and Communications 137, 153803, 2021 | 40 | 2021 |
| Design insights into RF/analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications VB Sreenivasulu, V Narendar International Journal of RF and Microwave Computer‐Aided Engineering 31 (12 …, 2021 | 36 | 2021 |
| Performance enhancement of FinFET devices with gate-stack (GS) high-K dielectrics for Nanoscale applications V Narendar Silicon 10 (6), 2419-2429, 2018 | 32 | 2018 |
| Design of high-performance digital logic circuits based on FinFET technology V Narendar, S Rai, RA Mishra International Journal of Computer Applications 41 (20), 2012 | 31 | 2012 |
| Circuit analysis and optimization of GAA nanowire FET towards low power and high switching VB Sreenivasulu, V Narendar Silicon 14 (16), 10401-10411, 2022 | 27 | 2022 |
| Junctionless gate-all-around nanowire FET with asymmetric spacer for continued scaling VB Sreenivasulu, V Narendar Silicon, 1-11, 2021 | 27 | 2021 |
| Investigation of short channel effects (SCEs) and analog/RF figure of merits (FOMs) of dual-material bottom-spacer ground-plane (DMBSGP) FinFET V Narendar, P Narware, V Bheemudu, B Sunitha Silicon 12, 2283-2291, 2020 | 26 | 2020 |
| A two-dimensional (2D) analytical surface potential and subthreshold current model for the underlap dual-material double-gate (DMDG) FinFET V Narendar, S Rai, S Tiwari Journal of Computational Electronics 15, 1316-1325, 2016 | 25 | 2016 |
| A three-dimensional (3D) analytical model for subthreshold characteristics of uniformly doped FinFET S Tripathi, V Narendar Superlattices and Microstructures 83, 476-487, 2015 | 25 | 2015 |
| p-Type trigate junctionless nanosheet MOSFET: analog/RF, linearity, and circuit analysis BS Vakkalakula, N Vadthiya ECS Journal of Solid State Science and Technology 10 (12), 123001, 2021 | 24 | 2021 |
| A two-dimensional (2D) analytical modeling and improved Short Channel performance of Graded-Channel gate-stack (GCGS) dual-material double-gate (DMDG) MOSFET N Vadthiya, S Tripathi, RBS Naik Silicon 10, 2399-2407, 2018 | 24 | 2018 |
| A novel bottom-spacer ground-plane (BSGP) FinFET for improved logic and analog/RF performance N Vadthiya, P Narware, V Bheemudu, B Sunitha AEU-International Journal of Electronics and Communications 127, 153459, 2020 | 20 | 2020 |
V. Bharath SreenivasuluMAHE, IIT Patna-Postdoc, NIT Warangal-PhD, UGC-NETCorreu electrònic verificat a iitp.ac.in
