| Edgebert: Sentence-level energy optimizations for latency-aware multi-task nlp inference T Tambe, C Hooper, L Pentecost, T Jia, EY Yang, M Donato, V Sanh, ... MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture …, 2021 | 112 | 2021 |
| Masr: A modular accelerator for sparse rnns U Gupta, B Reagen, L Pentecost, M Donato, T Tambe, AM Rush, GY Wei, ... 2019 28th International Conference on Parallel Architectures and Compilation …, 2019 | 63 | 2019 |
| Maxnvm: Maximizing dnn storage density and inference efficiency with sparse encoding and error mitigation L Pentecost, M Donato, B Reagen, U Gupta, S Ma, GY Wei, D Brooks Proceedings of the 52Nd Annual IEEE/ACM International Symposium on …, 2019 | 45 | 2019 |
| On-chip deep neural network storage with multi-level eNVM M Donato, B Reagen, L Pentecost, U Gupta, D Brooks, GY Wei Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 41 | 2018 |
| 9.8 A 25mm2 SoC for IoT Devices with 18ms Noise-Robust Speech-to-Text Latency via Bayesian Speech Denoising and Attention-Based Sequence-to-Sequence … T Tambe, EY Yang, GG Ko, Y Chai, C Hooper, M Donato, PN Whatmough, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 158-160, 2021 | 40 | 2021 |
| A 16nm 25mm2 SoC with a 54.5x Flexibility-Efficiency Range from Dual-Core Arm Cortex-A53 to eFPGA and Cache-Coherent Accelerators P Whatmough, SK Lee, M Donato, HC Hsueh, SL Xi, U Gupta, ... 2019 IEEE Symposium on VLSI Circuits, 2019 | 39 | 2019 |
| Nvmexplorer: A framework for cross-stack comparisons of embedded non-volatile memories L Pentecost, A Hankin, M Donato, M Hempstead, GY Wei, D Brooks arXiv preprint arXiv:2109.01188, 2021 | 29 | 2021 |
| CHIPKIT: An agile, reusable open-source framework for rapid test chip development PN Whatmough, M Donato, GG Ko, SK Lee, D Brooks, GY Wei IEEE Micro 40 (4), 32-40, 2020 | 21 | 2020 |
| Smiv: A 16-nm 25-mm² soc for iot with arm cortex-a53, efpga, and coherent accelerators SK Lee, PN Whatmough, M Donato, GG Ko, D Brooks, GY Wei IEEE Journal of Solid-State Circuits 57 (2), 639-650, 2021 | 19 | 2021 |
| A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic M Donato, F Cremona, W Jin, RI Bahar, W Patterson, A Zaslavsky, ... Proceedings of the great lakes symposium on VLSI, 39-44, 2012 | 17 | 2012 |
| A 16-nm soc for noise-robust speech and nlp edge ai inference with bayesian sound source separation and attention-based dnns T Tambe, EY Yang, GG Ko, Y Chai, C Hooper, M Donato, PN Whatmough, ... IEEE Journal of Solid-State Circuits 58 (2), 569-581, 2022 | 16 | 2022 |
| Fundamental thermal limits on data retention in low-voltage CMOS latches and SRAM E Rezaei, M Donato, WR Patterson, A Zaslavsky, RI Bahar IEEE Transactions on Device and Materials Reliability 20 (3), 488-497, 2020 | 16 | 2020 |
| Memti: Optimizing on-chip nonvolatile storage for visual multitask inference at the edge M Donato, L Pentecost, D Brooks, GY Wei IEEE Micro 39 (6), 73-81, 2019 | 15 | 2019 |
| Application-driven design exploration for dense ferroelectric embedded non-volatile memories MM Sharifi, L Pentecost, R Rajaei, A Kazemi, Q Lou, GY Wei, D Brooks, ... 2021 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2021 | 13 | 2021 |
| A 3mm2 Programmable Bayesian Inference Accelerator for Unsupervised Machine Perception using Parallel Gibbs Sampling in 16nm GG Ko, Y Chai, M Donato, PN Whatmough, T Tambe, RA Rutenbar, ... 2020 IEEE Symposium on VLSI Circuits, 1-2, 2020 | 13 | 2020 |
| Fully-CMOS Multi-Level Embedded Non-Volatile Memory Devices with Reliable Long-Term Retention for Efficient Storage of Neural Network Weights S Ma, M Donato, SK Lee, D Brooks, GY Wei IEEE Electron Device Letters, 2019 | 13 | 2019 |
| EdgeBERT: Optimizing On-chip inference for multi-task NLP T Tambe, C Hooper, L Pentecost, EY Yang, M Donato, V Sanh, AM Rush, ... arXiv preprint arXiv:2011.14203, 2020 | 12 | 2020 |
| Shot-Noise-Induced Failure in Nanoscale Flip-Flops—Part I: Numerical Framework P Jannaty, FC Sabou, ST Le, M Donato, RI Bahar, W Patterson, J Mundy, ... Electron Devices, IEEE Transactions on, 1-7, 0 | 11* | |
| Design of error-resilient logic gates with reinforcement using implications X Han, M Donato, RI Bahar, A Zaslavsky, W Patterson Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 191-196, 2016 | 6 | 2016 |
| A sub-threshold noise transient simulator based on integrated random telegraph and thermal noise modeling M Donato, RI Bahar, WR Patterson, A Zaslavsky IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 5 | 2017 |
Gu-Yeon WeiRobert and Suzanne Case Professor of EE and CS, Harvard UniversityVerified email at eecs.harvard.edu
